1. Field of the Invention
The present invention relates to automatic gain control (AGC) circuits. More particularly, the present invention relates to low jitter AGC circuits for telecommunication applications which are embodied in integrated circuits.
2. State of the Art
One of the requirements for telecommunication circuits is an AGC circuit which restores the amplitude of pulses which have been transmitted over a lossy medium such as a coaxial line, a twisted pair, or an optical fiber line. The data transmitted over these lines is usually of the form of an encoded bit stream which contains a limited number of zeros to provide energy for clock extraction from the input data spectrum.
A block diagram of a prior art AGC control loop with differential inputs and outputs is seen in FIG. 1. The AGC circuit 10 includes two differential amplifiers 12, 14, a peak detector 15, a current source 16, and a capacitor 18. The first differential amplifier 12 receives the differential input signal INP, INN, and amplifies the signal according to a feedback control signal Vctrl. The differential output of amplifier 12 is fed to a fixed gain differential amplifier 14 which further boosts the signal and provides a differential output signal OUTP, OUTN. The differential output signals are fed back to the peak detector 15 which compares the level of the signals to a reference voltage and generates correction pulses. The correction pulses generated by the peak detector 15 are then fed to the capacitor 18 which is coupled between a ground voltage and the control input of the differential amplifier 12, thereby closing the feedback loop. The capacitor 18 stores the charge, and the voltage on the capacitor built up due to the stored charge effectively controls the amplification of amplifier 12. In order to permit the AGC loop to respond to changes in the input signal level, a discharge mechanism in the form of the current source 16 is provided between the the plates of capacitor 18.
With the prior art AGC circuit 10 as shown in FIG. 1, any non-DC signals which appear at the capacitor output (i.e., Vctrl) will amplitude modulate the output signals (OUTP, OUTN), and will cause jitter on the recovered data signal. Also, with the prior art AGC circuit 10, the spectral content of the signal appearing on the control voltage will be directly related to the number of zeros in the data stream. The waveform on the control voltage will appear as a sawtooth wave with a period T defined approximately according to: EQU T=(1+#of zeros)R
where R is the data repetition rate. In other words, where the input data signal includes many zeros, the charge on capacitor 18 will drain, and will force Vcrtl low. As a result, the gain of AGC amplifier 12 will be substantially boosted, which will in turn gradually build up charge on the capacitor 18 and bring the gain of the signal back to desired levels. In the interim, however, undesirably large swings in the voltage of the output signals OUTP and OUTN will occur.
Those skilled in the art will appreciate that the control voltage is ideally a DC signal, since any AC signals which are present will cause amplitude modulation of the output signal. To simplify integration of the charge storage element, the frequency of the AC signals appearing on the control voltage should be as high as possible relative to the data rate. However, with the prior art AGC circuits, the minimum period of the AC signals will always be less than the data rate since there will always be zeros in the data stream. While it is possible to filter these pulses with an additional low pass filter, the time constant of the filter (which would typically require a large capacitor) would make integration of the circuit difficult and/or expensive in terms of IC chip area.